Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs).\nHowever, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we\npresent a two-clock-cycle latency NoC micro architecture. An efficient request masking technique is proposed to combine virtual\nchannel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area\noverhead, operating frequency, and quality-of-service (QoS).We evaluate our NoC against CONNECT, an open source low latency\nNoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our\nNoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%?20%\nhigher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover,\nthe proposed NoC router achieves 2.3 times better performance compared to CONNECT.
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